Job Description and Requirements
Synopsys is seeking an enthusiastic and creative Software Engineer (m / f) to strengthen its engineering team in Leuven, Belgium.
At this site, Synopsys develops design tools for application-specific processors (ASIPs) and provides related customer support.
Specifically, our ASIP Designer tool-suite is used by customers worldwide in the development of systems-on-chip (SoC) for 5G wireless communication, deep learning, artificial intelligence, autonomous driving, biomedical applications, the internet of things, and similar.
The Role :
As a Software Engineer you will maintain and enhance existing design tools (written in C++), and contribute to the development of new tools for ASIPs.
You will also assist our Application Engineers with expert advice to guide customers in developing, implementing, and verifying advanced systems-
on-chip for exciting next generation products.
The current job opening is in the ASIP modeling and implementation team, in relation to the hardware description language (HDL) generator.
The HDL tool generates register transfer level (RTL) code (Verilog or VHDL) to be synthesized into a physical HW implementation.
The quality of the generated RTL code is crucial for power, performance, and area of the resulting chip, so it must be benchmarked using physical synthesis tools.
The generated RTL code also needs to be verifiable in standard SystemVerilog / UVM verification flows.
Requirements : To apply for this role
To apply for this role
Synopsys offers a stimulating work environment with international contacts, flexibility and an attractive compensation package.
You will work with highly professional and motivated colleagues who value your opinion.
If this job description sounds interesting, we look forward to hearing from you!