Our client, a leading global telecommunication company are recruiting for a Senior Digital IC Design Engineer to join their business in Belgium.
This role includes technical hands-on expertise and excellent team skills; together with his / her team members, this candidate targets high and challenging standards on technical performance, product and process quality and project schedule.
MSEE with min 3 to 5 years of industrial experience designing for ASIC, PhD is a plus.
Synchronous Verilog / VHDL design targeted at ASIC’s :
Running a simulator (Cadence, Synopsys, Mentor), visualizing waveforms, general design analysis and debug
Knowledge of module, subsystem and toplevel verification :
Preferred experience with UVM / VMM / OVM flow
Coverage (automated and functional)
Assertion based verification (ABV)
Able to write implementation specification and define micro-architectures based on functional specification.
Knowledgeable about concepts such as pipelining and retiming.
Able to work in a Linux environment :
Python, Perl, TCL scripting
C / C++ coding and debug
Experience with revision control systems such as SVN, GIT, Perforce.
Experience with (the implementation of) simple DSP algorithms is a plus.
Excellent analytical skills.
Good communication skills.
Team-player and Result driven.
Continuous strive for improvement in circuits and process.
Detail oriented and determined.
Willing to relocate to Belgium.
Fluent in English (spoken and written)